Researchers have unveiled a cutting-edge power supply technology designed for 3D-integrated chips. This strategy employs a unique stacked architecture where processing units are positioned directly above layers of dynamic random access memory (DRAM).

To make this a reality, the team developed important technologies that focus on precise and rapid bonding methods as well as advanced adhesive solutions. These innovations aim to meet the high demands of modern computing applications that require increased memory bandwidth and reduced power supply noise.

From everyday gadgets like TVs to laptops and wearables, electronics have dramatically reshaped our lives. Innovations in semiconductor manufacturing and chip packaging have fueled this boom. However, with the rise of artificial intelligence and other advanced tech, the quest for faster and more energy-efficient processors is still ongoing.

The traditional system-in-package (SiP) methods, which arrange chips in a 2D layout using solder bumps, face size limitations, prompting the need for new chip integration technologies. Addressing this, scientists from the Institute of Science Tokyo have introduced a groundbreaking 2.5D/3D chip integration technique known as BBCube and developed three core technologies to facilitate its implementation.

The findings from their research were recently shared at the 2025 IEEE 75th Electronic Components and Technology Conference (ECTC), which took place from May 27 to May 30, 2025.

The research team, including Professors Norio Chujo and Takayuki Ohba, along with other experts from the WOW Alliance Heterogeneous and Functional Integration Unit at the Institute of Science Tokyo, initially created a face-down chip-on-wafer (COW) process to overcome the challenges of solder connections.

Utilizing inkjet technology and a special adhesive coating technique, they successfully bonded different chip sizes onto a 300 mm wafer with a tight chip-to-chip spacing of just 10 μm and a quick mount time of less than 10 milliseconds.

Chujo explained the efficiency of the COW process, stating, “We successfully fabricated over 30,000 chips of varying sizes on the wafer, achieving fast bonding speeds without any chip detachment failures.”

To support this high-speed COW process, the team tackled thermal stability issues related to stacking ultra-thin wafers. They designed a new adhesive, called DPAS300, with an organic-inorganic hybrid structure, which showed excellent adhesion and heat resistance in experiments.

Furthermore, to enhance BBCube’s memory bandwidth and power stability, the scientists implemented a 3D xPU-on-DRAM architecture supported by a new power distribution method. This involved embedding capacitors between the xPU and DRAM, creating redistribution layers on the wafer, and positioning through-silicon vias in wafer lanes and DRAM scribe lines.

Chujo highlighted the advantages of this innovative architecture, mentioning, “These improvements cut the energy needed for operation to just one-fifth to one-twentieth of what traditional systems require, while also keeping power supply noise under 50 mV.”

In summary, the integration technologies developed by the researchers at the Institute of Science Tokyo have the potential to revolutionize future computing architectures.